Product Description
This digital document is an article from XDSL News, published by Information Gatekeepers, Inc. on August 1, 2008. The length of the article is 367 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available immediately after purchase. You can view it with any web browser.

Citation Details
Title: Zhone Technologies selects Ikanos for broadband access equipment.(CONTRACTS)
Author: Gale Reference Team
Publication: XDSL News (Newsletter)
Date: August 1, 2008
Publisher: Information Gatekeepers, Inc.
Volume: 12Issue: 8Page: 6(2)

Distributed by Gale, a part of Cengage Learning ... Read more

Product Description

Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in an SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come.

Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips.
In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called "cores") that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality.

From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques. Features of the Third Edition:

• Up to date;
• State of the art;
• Reuse as a solution for circuit designers;
• A chronicle of "best practices";
• All chapters updated and revised;
• Generic guidelines - non tool specific;
• Emphasis on hard IP and physical design.

Customer Reviews (4)

Not worth the money
Don't spend your money on this book, there is a lot of repetive stuff in it.Also, if you already work in the field of ASIC design, you will not learn much in this book, trust me.

Very useful in practice
This book pointed out many design problems that I just met before. Designer could avoid many of them by following the guidelines in this book. I think it would help me a lot in my design work. Thanks to the authors.

Recommend it to every designer as a handbook
The guidelines are not difficult to understand, and you may have the pieces here and there. But this book has a broad coverage. I got this book by luck draw at SNUG. Didn't pay attention at first until I read it. Very well organized, very accurate description of the real feelings of doing a real chip. The methodology it talks about is not limited to "reuse". I suggest the auther change the title for next edition.

Great baseline text for VLSI designers of all stripes
I really liked this book and found its rules and guidelines very useful. Many of the guidelines are common sense, but it is still very appropriate to have them codified in a single textbook. Practitioners of full-customapproaches to IC design will complain that this is an "ASIC"book. It does have some rules that folks from that background will findhard to swallow (eg, no latches, no gated clocks). But 70% of the book isstill applicable to full custom design and will result in faster re-use offull custom cores. The book gets off to a fairly wooly start but becomessubstantial with the RTL Coding Guidelines chapter. From then on, itsreally solid stuff. This is a good book for the times. With much discussionof design re-use and transferable intelectual property in the chipindustry, it has all the hallmarks of becoming a 'bible' book for ICdesigners of all stripes. ... Read more